Low power low noise amplifier

ABSTRACT

The present invention relates to a low power low noise amplifier, more particularly to the low power low noise amplifier composed with low power by sharing the bias current.  
     The present invention is composed of cascode structure which consists of common source transistor and common gate transistor connecting with common source transistor, inverter type structure connecting with common source transistor and structure improving the third-order intermodulation component using the parallel connected common source transistor and common gate transistor.  
     The present invention provides a low noise amplifier gives high power gain without increasing power consumption by sharing the bias current.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention related to a low power low noise amplifier,more particularly to the low power low noise amplifier which gives highpower gain with low power consumption by improving the conventional lownoise amplifier.

[0003] 2. Description of the Related Art

[0004] A low noise amplifier (LNA), which is used for RF receiver in awireless communication application, is used necessarily at a receiverfor obtaining power gain and decreasing noise factor(NF).

[0005] A RF system in a wireless communication application requires alow power structure especially for portable communication system.Therefore, it should be designed to be consumed the least power withinthe range which can be satisfied in.

[0006] However, the conventional low noise amplifier needs high powerconsumption at the RF receiver to satisfy the required power gain andcharacteristics compared to the present invention. The conventional LNAuses one unit common source amplifier structure showing as FIG. 1 orcascode amplifier structure showing as FIG. 2.

SUMMARY OF THE INVENTION

[0007] However, in the conventional amplifier structure, high power gaincan not be obtained due to low transconductance when the amplifier isoperated with low power using low bias current. Therefore, it is limitedto obtain high enough power gain at RF receiver with low power.

[0008] So, the present invention contrived to solve the above mentionedproblem is proposed to improve linearity and to obtain high power gainwith low power.

[0009] To reach the proposed purpose, the same power gain can beobtained by designing a low power amplifier to share the bias current asthe power gain by designing two stages common source amplifier as onestage amplifier.

[0010] The present invention is characterized by having a structureimproving the linearity and preventing minimizing the linearity uponincreasing power gain and improving the linearity by using an invertertype structure amplifier and the third order intermodulation componentusing the parallel connected common source transistor and common gatetransistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0011]FIG. 1 is a low noise amplifier structure which has theconventional common source configuration.

[0012]FIG. 2 is a low noise amplifier structure which has theconventional cascode configuration.

[0013]FIG. 3 is a circuit diagram of a low power low noise amplifieraccording to the first embodiment of the present invention.

[0014]FIG. 4 is a circuit diagram of a low power low noise amplifieraccording to the second embodiment of the present invention.

[0015]FIG. 5 is a circuit diagram of a low power low noise amplifieraccording to the third embodiment of the present invention.

[0016]FIG. 6 is a circuit diagram of a low power low noise amplifieraccording to the fourth embodiment of the present invention.

DETAILED DESCRIPTION OF THE EMBODIMENTS

[0017] Hereafter, an embodiment according to the present invention isdescribed in detail by referring to accompanying drawings.

[0018]FIG. 3 is the first embodiment of the present invention.

[0019] Herein, inductors L_(g) and L_(s) are used for matching inputimpedance, and inductor L_(d) and capacitor C₃ are used for matchingoutput impedance.

[0020] Herein, the capacitor C₂ is a bypass capacitor. So, source ofcommon source component transistor M₃ is bypassed by the C₂.

[0021] In this structure, the signal amplified as much the gain bycascode structure composed of transistors M₁ and M₂ is amplified throughcoupling to the gate of common source transistor M₃ by capacitor C₁.

[0022] The entire gain is obtained by multiplying of the gain of cascodeamplifier and common source amplifier. Therefore, the high power gaincan be obtained compared to the conventional common source amplifier orcascode amplifier.

[0023] Herein, transistors M₁ and M₂ are operated as cascode amplifier,and transistor M₃ is used as common source amplifier, and there is noincrease of the bias current because the bias current is shared.Therefore, higher power gain can be obtained when the same power isused. Also, lower power is consumed to obtain the same power gain.

[0024]FIG. 4 is the second embodiment of the present invention.

[0025] In this structure, the signal amplified by common sourcecomponent transistor M₁ is coupled to gate of transistor M₂ by capacitorC₁ and is output after being amplified as much as the gain by thecascode structure composed of the said transistors M₁ and M₂.

[0026] Herein, transistor M₁ is operated as a common source amplifier,and transistors M₂ and M₃ are operated as a cascode amplifier, andbecause the bias current is shared, there is no increase of the biascurrent. In this case, source of transistor M₂ is bypassed by capacitorC₂.

[0027] The entire gain is obtained by multiplying of the gain of cascodeamplifier and common source amplifier. Therefore, the high power gaincan be obtained compared to the conventional common source amplifier orcascode amplifier.

[0028]FIG. 5 is the third embodiment of the present invention.

[0029] In this structure, the signal amplified by transistor M₁ iscoupled by N-type transistors M₂ and P-type transistor M₃ and then isoutput.

[0030] This structure gives higher power gain by sharing the biascurrent compared to the conventional structure and compensates linearitygot worse in the high power gain structure.

[0031] The inverter type amplifier unit composed of transistors M₂ andM₃ have good linearity by push-pull operating, and it increases thelinearity of the entire low noise amplifier.

[0032] Also, by sharing the bias current, higher power gain can beobtained with low current compared to the conventional common sourceamplifier or inverter type amplifier.

[0033]FIG. 6 is the fourth embodiment of the present invention.

[0034] The signal amplified by common source transistor M₁ is coupled bycapacitor C₁ and then is applied to the gate of the common sourcetransistor M₂ and the source of the common gate transistor M₃.

[0035] The drains of the common source transistor M₂ and common gatetransistor M₃ are connected by output, and the third-orderintermodulation outputs of transistors M₂ and M₃ have opposite polarityeach other so that the total third-order intermodulation is cancelled.

[0036] Here, the signal amplified by common source transistor M₂ andcommon gate transistor M₃ has 180 degree phase difference, so, theentire linearity can be improved by satisfying the condition which isminimizing the decrease of fundamental component by adjusting biascurrent and transistor size meanwhile maximizing the cancellation of thethird-order harmonic component.

[0037] As mentioned above, the present invention provides the higherpower gain with one stage amplifier and the low power design by sharingthe bias current.

[0038] Also, the present invention can improve the linearity bypreventing declining the linearity due to high power gain.

What is claimed is:
 1. A low power low noise amplifier characterized wherein a signal amplified as much as a gain by cascode transistors M₁ and M₂ is amplified after being coupled by capacitor C₁ to a gate of a common source transistor M₃, and the said transistors M₁, M₂, and M₃ share a bias current.
 2. A low power low noise amplifier characterized wherein a signal amplified by a common source transistor M₁ is amplified as much as a gain by cascode transistors M₂ and M3 after being coupled by a gate capacitor C₁, and the said transistors M₁, M2, and M₃ share a bias current.
 3. A low power low noise amplifier characterized wherein a signal amplified by a common source transistor M₁ is amplified by an inverter type composed of N-type transistor M₂ and P-type transistor M₃ and is output, and the said transistors M₁, M₂, and M₃ share a bias current.
 4. A low power low noise amplifier characterized wherein a signal amplified by a common source transistor M₁ is amplified after being coupled by capacitor C₁ and then being applied to a gate of a common source transistor M₂ and a source of a common gate transistor M₃, and a third-order intermodulation output of transistors M₂ and M₃ have opposite polarity each other so that the total third-order intermodulation is cancelled. And the said transistors M₁, M₂, and M₃ share a bias current. 